`include "define.v"
module IDS_EX
(
    input   wire                clk,
    input   wire                rstn,
    input   wire                flush,
    input   wire                stall,
    //
    
    //
    input   wire                IDS_EX_BUBBLE_FLAG_i,
    input   wire                IDS_EX_ILLEGAL_INSTR_FLAG_i,
    //
    input   wire    [63:00]     IDS_EX_PC_i,
    input   wire    [31:00]     IDS_EX_INSTR_i,
    input   wire    [02:00]     IDS_EX_FUNCT3_i,
    //
    input   wire                IDS_EX_INSTR_JALR_i,
    input   wire                IDS_EX_INSTR_LOAD_i,
    input   wire                IDS_EX_INSTR_STORE_i,
    input   wire                IDS_EX_INSTR_SYSTEM_i,
    input   wire                IDS_EX_INSTR_BRANCH_i,
    input   wire                IDS_EX_BRANCH_PREDIC_RES_i,
    input   wire    [63:00]     IDS_EX_BRANCH_RESERVE_ADDR_i,
    //
    input   wire                IDS_EX_GPR_WRITE_BACK_EN_i,
    input   wire    [04:00]     IDS_EX_GPR_WRITE_BACK_ID_i,
    input   wire                IDS_EX_GPR_WRITE_BACK_FROM_ALU_i,
    input   wire                IDS_EX_GPR_WRITE_BACK_FROM_LSU_i,
    input   wire                IDS_EX_GPR_WRITE_BACK_FROM_MDU_i,
    input   wire    [03:00]     IDS_EX_DISP_TARGET_i,
    input   wire                IDS_EX_CSR_WRITE_BACK_EN_i,
    input   wire    [11:00]     IDS_EX_CSR_WRITE_BACK_ID_i,  
    // 
    input   wire    [01:00]     IDS_EX_ALU_SHIFT_MODE_i,
    input   wire    [10:00]     IDS_EX_ALU_OP_i,
    input   wire    [08:00]     IDS_EX_MDU_OP_i,
      
    //
    input   wire    [63:00]     IDS_EX_SHIFT2_i,
    input   wire    [32:00]     IDS_EX_ADD_RES_L_i   ,
    input   wire    [31:00]     IDS_EX_ADD_RES_H_i   ,
    input   wire    [32:00]     IDS_EX_SUB_RES_L_i   ,   
    input   wire    [31:00]     IDS_EX_SUB_RES_H_i   ,
    input   wire                IDS_EX_SUBU_RES_L_i  ,
    input   wire    [31:00]     IDS_EX_SUBU_RES_H_i  ,
    input   wire    [63:00]     IDS_EX_OPERAND1_i,
    input   wire    [63:00]     IDS_EX_OPERAND2_i,
    input   wire    [63:00]     IDS_EX_RS1_DATA_i   ,
    input   wire    [63:00]     IDS_EX_RS2_DATA_i   ,            
    input   wire    [63:00]     IDS_EX_JALR_OFFSET_i,
    input   wire    [63:00]     IDS_EX_CSR_DATA_i,
//--------------------------------------------------------
    output  reg                 IDS_EX_BUBBLE_FLAG_o,
    output  reg                 IDS_EX_ILLEGAL_INSTR_FLAG_o,                   
    //
    output  reg     [63:00]     IDS_EX_PC_o,
    output  reg     [02:00]     IDS_EX_FUNCT3_o,
    output  reg     [31:00]     IDS_EX_INSTR_o,                                    
    //
    output  reg                 IDS_EX_INSTR_JALR_o,
    output  reg                 IDS_EX_INSTR_LOAD_o,                                    
    output  reg                 IDS_EX_INSTR_STORE_o, 
    output  reg                 IDS_EX_INSTR_SYSTEM_o,                                     
    output  reg                 IDS_EX_INSTR_BRANCH_o,
    output  reg                 IDS_EX_BRANCH_PREDIC_RES_o,
    output  reg     [63:00]     IDS_EX_BRANCH_RESERVE_ADDR_o,                   
    //
    output  reg                 IDS_EX_GPR_WRITE_BACK_EN_o,                   
    output  reg     [04:00]     IDS_EX_GPR_WRITE_BACK_ID_o,                   
    output  reg                 IDS_EX_GPR_WRITE_BACK_FROM_ALU_o,
    output  reg                 IDS_EX_GPR_WRITE_BACK_FROM_LSU_o,
    output  reg                 IDS_EX_GPR_WRITE_BACK_FROM_MDU_o,
    output  reg                 IDS_EX_CSR_WRITE_BACK_EN_o,                   
    output  reg     [11:00]     IDS_EX_CSR_WRITE_BACK_ID_o, 
    output  reg     [03:00]     IDS_EX_DISP_TARGET_o,                    
    // 
    output  reg     [01:00]     IDS_EX_ALU_SHIFT_MODE_o, 
    output  reg     [10:00]     IDS_EX_ALU_OP_o,
    output  reg     [08:00]     IDS_EX_MDU_OP_o,                    
    //
    output  reg     [63:00]     IDS_EX_SHIFT2_o,
    output  reg     [32:00]     IDS_EX_ADD_RES_L_o   ,
    output  reg     [31:00]     IDS_EX_ADD_RES_H_o   ,
    output  reg     [32:00]     IDS_EX_SUB_RES_L_o   ,   
    output  reg     [31:00]     IDS_EX_SUB_RES_H_o   ,
    output  reg                 IDS_EX_SUBU_RES_L_o  ,
    output  reg     [31:00]     IDS_EX_SUBU_RES_H_o  ,
    output  reg     [63:00]     IDS_EX_OPERAND1_o,                   
    output  reg     [63:00]     IDS_EX_OPERAND2_o,
    output  reg     [63:00]     IDS_EX_RS1_DATA_o   ,
    output  reg     [63:00]     IDS_EX_RS2_DATA_o   ,            
    output  reg     [63:00]     IDS_EX_JALR_OFFSET_o,                                   
    output  reg     [63:00]     IDS_EX_CSR_DATA_o                   
);
    always @(posedge clk ) begin
        if (!rstn | flush) begin
            IDS_EX_BUBBLE_FLAG_o                                         <=  1'b1;        // flush后产生气泡 
            IDS_EX_ILLEGAL_INSTR_FLAG_o                                  <=  1'b0;          
            IDS_EX_INSTR_o                                               <=  `BUBBLE;
            IDS_EX_PC_o                                                  <=  64'b0;
            IDS_EX_FUNCT3_o                                              <=  3'b0; 
            IDS_EX_INSTR_JALR_o                                          <=  1'b0;                        
            IDS_EX_INSTR_LOAD_o                                          <=  1'b0;                    
            IDS_EX_INSTR_STORE_o                                         <=  1'b0; 
            IDS_EX_INSTR_SYSTEM_o                                        <=  1'b0;                       
            IDS_EX_INSTR_BRANCH_o                                        <=  1'b0; 
            IDS_EX_BRANCH_PREDIC_RES_o                                   <=  1'b0;
            IDS_EX_BRANCH_RESERVE_ADDR_o                                 <=  64'b0;             
            IDS_EX_GPR_WRITE_BACK_EN_o                                   <=  1'b0;      
            IDS_EX_GPR_WRITE_BACK_ID_o                                   <=  5'b0;
            IDS_EX_GPR_WRITE_BACK_FROM_ALU_o                             <=  1'b0;
            IDS_EX_GPR_WRITE_BACK_FROM_LSU_o                             <=  1'b0;
            IDS_EX_GPR_WRITE_BACK_FROM_MDU_o                             <=  1'b0;      
            IDS_EX_DISP_TARGET_o                                         <=  4'b0;
            IDS_EX_CSR_WRITE_BACK_EN_o                                   <=  1'b0;      
            IDS_EX_CSR_WRITE_BACK_ID_o                                   <=  12'b0;
            IDS_EX_ALU_SHIFT_MODE_o                                      <=  2'b00;                 
            IDS_EX_ALU_OP_o                                              <=  9'b0;
            IDS_EX_MDU_OP_o                                              <=  9'b0;
            IDS_EX_SHIFT2_o                                              <=  64'b0; 
            IDS_EX_ADD_RES_L_o                                           <=  33'b0;
            IDS_EX_ADD_RES_H_o                                           <=  32'b0;
            IDS_EX_SUB_RES_L_o                                           <=  33'b0;   
            IDS_EX_SUB_RES_H_o                                           <=  32'b0;
            IDS_EX_SUBU_RES_L_o                                          <=  1'b0;
            IDS_EX_SUBU_RES_H_o                                          <=  32'b0;           
            IDS_EX_OPERAND1_o                                            <=  64'b0;               
            IDS_EX_OPERAND2_o                                            <=  64'b0;               
            IDS_EX_RS1_DATA_o                                            <=  64'b0;
            IDS_EX_RS2_DATA_o                                            <=  64'b0;            
            IDS_EX_JALR_OFFSET_o                                         <=  64'b0;                    
            IDS_EX_CSR_DATA_o                                            <=  64'b0;        
        end
        else if( stall ) begin
            IDS_EX_BUBBLE_FLAG_o                                         <=  IDS_EX_BUBBLE_FLAG_o; 
            IDS_EX_ILLEGAL_INSTR_FLAG_o                                  <=  IDS_EX_ILLEGAL_INSTR_FLAG_o;                  
            IDS_EX_INSTR_o                                               <=  IDS_EX_INSTR_o;
            IDS_EX_PC_o                                                  <=  IDS_EX_PC_o;
            IDS_EX_FUNCT3_o                                              <=  IDS_EX_FUNCT3_o;
            IDS_EX_INSTR_JALR_o                                          <=  IDS_EX_INSTR_JALR_o;                                
            IDS_EX_INSTR_LOAD_o                                          <=  IDS_EX_INSTR_LOAD_o;                    
            IDS_EX_INSTR_STORE_o                                         <=  IDS_EX_INSTR_STORE_o;
            IDS_EX_INSTR_SYSTEM_o                                        <=  IDS_EX_INSTR_SYSTEM_o;             
            IDS_EX_INSTR_BRANCH_o                                        <=  IDS_EX_INSTR_BRANCH_o; 
            IDS_EX_BRANCH_PREDIC_RES_o                                   <=  IDS_EX_BRANCH_PREDIC_RES_o ;
            IDS_EX_BRANCH_RESERVE_ADDR_o                                 <=  IDS_EX_BRANCH_RESERVE_ADDR_o;             
            IDS_EX_GPR_WRITE_BACK_EN_o                                   <=  IDS_EX_GPR_WRITE_BACK_EN_o;      
            IDS_EX_GPR_WRITE_BACK_ID_o                                   <=  IDS_EX_GPR_WRITE_BACK_ID_o; 
            IDS_EX_GPR_WRITE_BACK_FROM_ALU_o                             <=  IDS_EX_GPR_WRITE_BACK_FROM_ALU_o;
            IDS_EX_GPR_WRITE_BACK_FROM_LSU_o                             <=  IDS_EX_GPR_WRITE_BACK_FROM_LSU_o;
            IDS_EX_GPR_WRITE_BACK_FROM_MDU_o                             <=  IDS_EX_GPR_WRITE_BACK_FROM_MDU_o;     
            IDS_EX_DISP_TARGET_o                                         <=  IDS_EX_DISP_TARGET_o;  
            IDS_EX_CSR_WRITE_BACK_EN_o                                   <=  IDS_EX_CSR_WRITE_BACK_EN_o;      
            IDS_EX_CSR_WRITE_BACK_ID_o                                   <=  IDS_EX_CSR_WRITE_BACK_ID_o; 
            IDS_EX_ALU_SHIFT_MODE_o                                      <=  IDS_EX_ALU_SHIFT_MODE_o;                 
            IDS_EX_ALU_OP_o                                              <=  IDS_EX_ALU_OP_o;
            IDS_EX_MDU_OP_o                                              <=  IDS_EX_MDU_OP_o;
            IDS_EX_SHIFT2_o                                              <=  IDS_EX_SHIFT2_o;
            IDS_EX_ADD_RES_L_o                                           <=  IDS_EX_ADD_RES_L_o ;
            IDS_EX_ADD_RES_H_o                                           <=  IDS_EX_ADD_RES_H_o ;
            IDS_EX_SUB_RES_L_o                                           <=  IDS_EX_SUB_RES_L_o ;
            IDS_EX_SUB_RES_H_o                                           <=  IDS_EX_SUB_RES_H_o ;
            IDS_EX_SUBU_RES_L_o                                          <=  IDS_EX_SUBU_RES_L_o;
            IDS_EX_SUBU_RES_H_o                                          <=  IDS_EX_SUBU_RES_H_o;              
            IDS_EX_OPERAND1_o                                            <=  IDS_EX_OPERAND1_o;               
            IDS_EX_OPERAND2_o                                            <=  IDS_EX_OPERAND2_o;               
            IDS_EX_RS1_DATA_o                                            <=  IDS_EX_RS1_DATA_o;
            IDS_EX_RS2_DATA_o                                            <=  IDS_EX_RS2_DATA_o;            
            IDS_EX_JALR_OFFSET_o                                         <=  IDS_EX_JALR_OFFSET_o;                    
            IDS_EX_CSR_DATA_o                                            <=  IDS_EX_CSR_DATA_o;        
        end
        else    begin
            IDS_EX_BUBBLE_FLAG_o                                         <=  IDS_EX_BUBBLE_FLAG_i; 
            IDS_EX_ILLEGAL_INSTR_FLAG_o                                  <=  IDS_EX_ILLEGAL_INSTR_FLAG_i;                 
            IDS_EX_INSTR_o                                               <=  IDS_EX_INSTR_i;
            IDS_EX_PC_o                                                  <=  IDS_EX_PC_i;
            IDS_EX_FUNCT3_o                                              <=  IDS_EX_FUNCT3_i;
            IDS_EX_INSTR_JALR_o                                          <=  IDS_EX_INSTR_JALR_i;                                
            IDS_EX_INSTR_LOAD_o                                          <=  IDS_EX_INSTR_LOAD_i;                    
            IDS_EX_INSTR_STORE_o                                         <=  IDS_EX_INSTR_STORE_i;
            IDS_EX_INSTR_SYSTEM_o                                        <=  IDS_EX_INSTR_SYSTEM_i;                        
            IDS_EX_INSTR_BRANCH_o                                        <=  IDS_EX_INSTR_BRANCH_i;
            IDS_EX_BRANCH_PREDIC_RES_o                                   <=  IDS_EX_BRANCH_PREDIC_RES_i ;
            IDS_EX_BRANCH_RESERVE_ADDR_o                                 <=  IDS_EX_BRANCH_RESERVE_ADDR_i;              
            IDS_EX_GPR_WRITE_BACK_EN_o                                   <=  IDS_EX_GPR_WRITE_BACK_EN_i;      
            IDS_EX_GPR_WRITE_BACK_ID_o                                   <=  IDS_EX_GPR_WRITE_BACK_ID_i;
            IDS_EX_GPR_WRITE_BACK_FROM_ALU_o                             <=  IDS_EX_GPR_WRITE_BACK_FROM_ALU_i;
            IDS_EX_GPR_WRITE_BACK_FROM_LSU_o                             <=  IDS_EX_GPR_WRITE_BACK_FROM_LSU_i;
            IDS_EX_GPR_WRITE_BACK_FROM_MDU_o                             <=  IDS_EX_GPR_WRITE_BACK_FROM_MDU_i;      
            IDS_EX_DISP_TARGET_o                                         <=  IDS_EX_DISP_TARGET_i;  
            IDS_EX_CSR_WRITE_BACK_EN_o                                   <=  IDS_EX_CSR_WRITE_BACK_EN_i;      
            IDS_EX_CSR_WRITE_BACK_ID_o                                   <=  IDS_EX_CSR_WRITE_BACK_ID_i;
            IDS_EX_ALU_SHIFT_MODE_o                                      <=  IDS_EX_ALU_SHIFT_MODE_i;                   
            IDS_EX_ALU_OP_o                                              <=  IDS_EX_ALU_OP_i;
            IDS_EX_MDU_OP_o                                              <=  IDS_EX_MDU_OP_i;
            IDS_EX_SHIFT2_o                                              <=  IDS_EX_SHIFT2_i;
            IDS_EX_ADD_RES_L_o                                           <=  IDS_EX_ADD_RES_L_i ;
            IDS_EX_ADD_RES_H_o                                           <=  IDS_EX_ADD_RES_H_i ;
            IDS_EX_SUB_RES_L_o                                           <=  IDS_EX_SUB_RES_L_i ;
            IDS_EX_SUB_RES_H_o                                           <=  IDS_EX_SUB_RES_H_i ;
            IDS_EX_SUBU_RES_L_o                                          <=  IDS_EX_SUBU_RES_L_i ; 
            IDS_EX_SUBU_RES_H_o                                          <=  IDS_EX_SUBU_RES_H_i ;             
            IDS_EX_OPERAND1_o                                            <=  IDS_EX_OPERAND1_i;               
            IDS_EX_OPERAND2_o                                            <=  IDS_EX_OPERAND2_i; 
            IDS_EX_RS1_DATA_o                                            <=  IDS_EX_RS1_DATA_i;
            IDS_EX_RS2_DATA_o                                            <=  IDS_EX_RS2_DATA_i;
            IDS_EX_JALR_OFFSET_o                                         <=  IDS_EX_JALR_OFFSET_i;                                         
            IDS_EX_CSR_DATA_o                                            <=  IDS_EX_CSR_DATA_i;
        end  
    end

endmodule